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李秋瑩

​​​​李秋瑩老師個人照片李秋瑩 教授

分機 : 5706

Mail : PP010@mail.lhu.edu.tw

學歷:長庚大學電機工程研究所博士

【專長 】

  • Finite field arithmetic
  • Channel coding
  • Cryptosystems
  • Fault Tolerant Computing

【學歷】

  • 長庚大學電機工程研究所博士(1998/9 ~ 2001/6)
  • 中原大學電機工程研究所碩士(1991/9 ~ 1994/1)
  • 中原大學醫學工程學系學士(1981/9 ~ 1985/6)

【經歷】

  • 龍華科技大學資訊與網路工程系專任助理教授(94/8 ~ 迄今)
  • 龍華科技大學資訊與網路工程系兼任助理教授(93/9 ~ 94/7)
  • 清雲科技大學電子系兼任助理教授(90/9 ~ 93/7)
  • 中華電信研究所(77/9 ~ 94/8)

【證照】

  • 七十七年度「交通部事業電信人員高級技術人員特考」及格
  • 八十九年度獲頒「中華民國斐陶斐榮譽學會」榮譽會員

【研究計畫】

計畫名稱(本會補助者請註明編號) Name of Plan (please indicate subsidy serial number) 起迄年月
year
補助或委託機構
Subsidy or Commission Unit
執行情形
Execution State
以Hankel乘法矩陣為基礎研究多基底的有限場GF(2m)乘法演算法
(NSC 94-2218-E-262-003)Research of multi- bases limited field GF (2m) multiplication algorithm based on Hankel multiplication matrix (NSC 94-2218-E-262-003)
2005.11.01 ~
2006.07.31
國科會
National Science Council
執行中
Executing
有限場算數運算理論 : 通用與展延的乘法演算法與其容錯電路設計
(1/2)Limited field arithmetic operation theory: General and Extending multiplication algorithm and  fault-tolerant circuit design (1/2)
2006.08.01 ~
2007.07.31
國科會
National Science Council
申請中
Applying
推動教學卓越績效考核計畫
Impelling Remarkable Performance Approval Plan of Teaching
2006.05.01 ~
2008.12.31
教育部
Ministry of Education
申請中
Applying

【著作】

  • 碩博論文:
    • 碩士論文:Master Paper
      Studying of the binary code with the step by step error trapping decoding
    • 博士論文:Doctor Paper
      Low-Complexity Bit-Parallel Systolic Architecture for Computing Multiplication and Exponentiation over Finite Field GF(2m)
  • 期刊論文:
    • Che Wun Chiou and Chiou-Yng Lee, "Sequential type-1 optimal normal basis multiplier and multiplicative inverse in GF(2m)," (revised) Computers & Electrical Engineering, 2006 (SCI)
    • Che Wun Chiou, Chiou-Yng Lee and Jim-Min Lin, "Finite field polynomial multiplier with linear feedback shift register," (revised) Tamkang Journal of Science and Engineering, 2006 (EI)
    • Chiou-Yng Lee and Che Wun Chiou, "New bit-parallel systolic architectures for computing multiplication, multiplicative inversion and division in GF(2m) under the polynomial basis and the normal basis," (revised)The Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, 2006 (SCI)
    • Che Wun Chiou and Chiou-Yng Lee, "Multiplexer implementation of low-complexity polynomial basis multiplier in GF(2m) using all one polynomial," (revised) Information Processing Letters, 2006 (SCI)
    • Chiou-Yng Lee, Jim-Min Lin and Che Wun Chiou, "Scalable and systolic architecture for computing double exponentaition over GF(2m)," (accepted) Acta Applicandae Mathematicae, 2006 (SCI)
    • Chiou-Yng Lee, Che Wun Chiou, An-Wen Deng and Jim-Min Lin, "Low-Complexity Bit-parallel systolic architectures for computing A(x)B2(x) over GF(2m)," (accepted) IEE Proceeding Circuits and Systems, 2006 (SCI)
    • Chiou-Yng Lee, Jenn-Shyong Horng and I-Chang Jou, "New dual-basis multiplier over GF(2m)," (accepted) Journal of Computer Science Technology, May 2006 (SCI)
    • Chiou-Yng Lee, Che Wun Chiou and Jim-Min Lin, "Concurrent error detection in polynomial basis multiplier over GF(2m)," (accepted) Journal of Electronic Testing: Theory and Applications, May 2006. (SCI)
    • Che Wun Chiou, Chiou-Yng Lee, An-Wen Deng and Jim-Min Lin, "Efficient VLSI implementation for Montgomery multiplication in GF(2m)," (accepted) Tamkang Journal of Science and Engineering, 2006 (EI)
    • Chiou-Yng Lee and Che Wun Chiou, "Flexible sequential multiplier in normal basis of GF(2m)," WSEAS Transactions on Computers, pp. 267-271, Issue 2, Volume 5, February 2006. (SCI)
    • Che Wun Chiou, Chiou-Yng Lee, An-Wen Deng and Jim-Min Lin, "Concurrent error detection in Montgomery multiplication over GF(2m)," IEICE Transactions on Fundamentals, vol. E89-A, no.2, pp. 566-574, 2006 (SCI)
    • Chiou-Yng Lee and Che Wun Chiou, "Low-complexity bit-parallel dual basis multipliers using the modified Booth's algorithm," Computers & Electrical Engineering, Vol. 31, No.7, pp.444-459, October. 2005 (SCI)
    • Chiou-Yng Lee and Che Wun Chiou, "Design of low-complexity bit-parallel systolic Hankel multipliers to implement multiplication in normal and dual bases of GF(2m)," IEICE Transactions on Fundamentals, vol. E88-A, no.11, pp. 3169-3179, Nov. 2005 (SCI)
    • Chiou-Yng Lee, Jenn-Shyong Horng and I-Chang Jou, "Low-complexity bit-parallel systolic Montgomery multipliers for special classes of GF(2m)," IEEE Transactions on Computers, vol. 54, no. 9, pp. 1061-1070, September 2005 (SCI)
    • Chiou-Yng Lee, Che Wun Chiou and Jim-Min Lin, "Concurrent error detection in a bit-parallel systolic multiplier for dual basis of GF(2m)," Journal of Electronic Testing: Theory and Applications, vol. 21, pp. 539-549, Sep. 2005. (SCI)
    • Che Wun Chiou and Chiou-Yng Lee, "Multiplexer-based double-exponentiation for normal basis of GF(2m)," Computers & Secure, vol. 24, pp. 83-86, January 2005 (SCI)
    • Chiou-Yng Lee and Chung-Jyi Chang, "Modular construction of bit-parallel systolic multipliers for a class of GF(2m)," WSEAS Transactions on Information Science & Applications, no. 1, vol. 2, pp. 1-8, January 2005. (SCI)
    • Chiou-Yng Lee and Che Wun Chiou, "Low-complexity sequential Berlekamp-like multiplier for all trinomials," WSEAS Transactions on Information Science & Applications, no. 1, vol. 2, pp. 9-13, January 2005. (SCI)
    • Chiou-Yng Lee, "K-bit-parallel systolic multiplier and squarer over GF(2m)," WSEAS Transactions on Computers, no. 1, vol. 4, pp. 1-7, January 2005. (SCI)
    • Chiou-Yng Lee and Jyhi-Kong Wey, "Evolution of intelligent network deployment in Taiwan's mobile networks," WSEAS Transactions on Computers, Issue 1, vol. 4, pp. 21-24, January 2005. (SCI)
    • Che Wun Chiou, Chiou-Yng Lee and Jim-Min Lin, "A survival array multiplier over GF(2m) under faults," WSEAS Transactions on Computers, no. 1, vol. 4, pp. 8-14, January 2005. (SCI)
    • Chiou-Yng Lee, "Systolic architectures for computing exponentiation and multiplication over GF(2m) using polynomial ring basis," Journal of LungHwa University, vol. 19, pp.87-98, September 2005
    • Chiou-Yng Lee, "Low-latency bit-parallel systolic multiplier for irreducible xm+xn+1 with gcd(m,n)=1," IEICE Transactions on Fundamentals, vol. E86-A, no.11, pp. 2844-2852, Nov. 2003 (SCI)
    • Chiou-Yng Lee, "Low-complexity bit-parallel systolic multiplier over GF(2m) using irreducible trinomials," IEE Proceeding Computer Digital technology, vol. 150, no. 1, pp. 39-42, Jan. 2003 (SCI)
    • 李秋瑩,"有限場GF(2m)之低複雜的心臟收縮陣列式乘法器,"國防通訊与電子期刊,第4期, pp.118-127, April, 2003
    • Chiou-Yng Lee, Erl-Huei Lu, and Lir-Fang Sun, "Low-complexity bit-parallel systolic architectures for computing AB2 +C in a class of finite field GF(2m)", IEEE Transactions on Circuits and Systems, part II, pp. 519-523, May 2001. (SCI)
    • Chiou-Yng Lee, Erl-Huei Lu, and Jau-Yien Lee, "Bit-parallel systolic multipliers for GF(2m) fields defined by all-one and equally-spaced polynomials," IEEE Transactions on Computers, pp. 385-393, May 2001. (SCI)
    • Erl-Huei Lu, Chiou-Yng Lee, Ron-Lon Tsai, "Decoding algorithm for DEC RS codes," Electronics Letters, vol. 36 no. 6 , pp. 546 -548, March 2000. (SCI)
    • Chung-Hsin Liu, Nen-Fu Huang, Chiou-Yng Lee, "Computation of AB2 multiplier in GF(2m) using an efficient low-complexity cellular Architecture," IEICE Transactions on Fundamentals, vol. E83-A, no. 12, pp. 2657-2662, Dec. 2000. (SCI)
    • J.C. Hong, S.H. Wu, L.T. Tao, L.T. Lee, Y.N. Tsao and C.Y. Lee, "The design and implementation of an ISDN signaling interworking unit (IWU) for providing interface services," TL Technical Journal, vol.22, no.1, pp.1-25, 1992.
  • 論文投稿中
    • Chiou-Yng Lee and Che Wun Chiou, "Low-Complexity bit-parallel multipliers for a class of GF(2m) based on modified booths algorithm," International Journal of Computers and Applications (EI)
    • Chiou-Yng Lee, Che Wun Chiou and Jim-Min Lin, "A Unified Parallel Systolic Multipliers over GF(2m) ," Journal of Computer Science Technology, 2006 (SCI)
    • Chiou-Yng Lee, Che Wun Chiou and Jim-Min Lin, "low-complexity parallel systolic architectures for computing multiplication and squaring over GF(2m)," IEICE Transactions on Fundamentals (SCI)
    • Che Wun Chiou, Chiou-Yng Lee and Jim-Min Lin, "Efficient systolic arrays for power-sum, inversion, and division in GF(2m)," IEEE Transactions on Circuits and Systems, part I (SCI)
    • Chiou-Yng Lee, "Low-complexity bit-parallel multipliers over GF(2m)," IEEE Transactions on Circuits and Systems, part I (SCI)
    • Chiou-Yng Lee, "Low-complexity bit-parallel Montgomery multipliers over GF(2m)," IEE Proceeding Circuits and Systems (SCI)
    • Che Wun Chiou and Chiou-Yng Lee, "A dual-field multiplier in GF(P) and GF(2m)," (submitted) International Journal of Electronics (SCI)
    • Chiou-Yng Lee and Che Wun Chiou, "Low-area double-basis multipliers And Inverters Over GF(2m)," International Journal of Electronics (SCI)
    • Chiou-Yng Lee and Che Wun Chiou, "Multiplexer-Based Bit-Parallel Systolic Multipliers over GF(2m)," Science in China Series F-Information Sciences(SCI)
    • Chiou-Yng Lee, "New Bit-Parallel systolic architectures for the modulo (2m-1) multiplication and addition," Tamkang Journal of Science and Engineering (EI)
  • 會議論文
    • Chi Hiang Chang, Houng Wei Chang, Tien-Lin Lee, Tsan Li Chen,Che Wun Chiou, Fu Hua Chou, Chiou-Yng Lee, "Concurrent Error Detection in Advanced Encryption Standard (AES)", 17th International Conference on Information Management, 2006
    • Houng Wei Chang, Chi Hiang Chang, Tsan Li Chen, Tien-Lin Lee, Che Wun Chiou, Fu Hua Chou, and Chiou-Yng Lee, "Anti Fault Based Cryptanalysis Design of Data Encryption Standard (DES)," 2006 International Conference of Digital Technology and Innovation Management, Shihtin Hsiang, Taipei Hsien, Taiwan, April 2006
    • Chiou-Yng Lee, Jenn-Shyong Horng and I-Chang Jou, "UParity-based on-line detection for a bit-parallel systolic dual-basis multiplier over GF(2UPUmUPU)U," 2006 IEEE International Symposium on Circuits and Systems, Greece (ISCS-2006), May 2006. (EI)
    • Tsan Li Chen, Tien-Lin Lee, Yih Ming Huang, Anne Lo, Che Wun Chiou, Chiou-Yng Lee, "Software fault-tolerant Montgomery modular multiplication algorithm in GF(2m)" 2005 Cross-Strait University President Symposium & Conference and Technology, pp.354-357, 2005.
    • Tien Lin Lee, Tsan Li Chen, Yih Ming Huang, Anne Lo, Che Wun Chiou, Chiou-Yng Lee, "Finite field multiplication for cryptography application in Embedded Linux system", 2005 Cross-Strait University President Symposium & Conference and Technology, pp.561-564, 2005
    • Che Wun Chiou and Chiou-Yng Lee, Yih Ming Huang, Anne Lo, Minor Chen and Tien-Lin Lee, "A array multiplier in GF(2m) fields for operands of any size," 2004 Cross Strait Tri-regional Radio Science and Wireless Technology Conference, pp. P19-22, Hsinchu, Taiwan, Sep. 2004.
    • Che Wun Chiou and Chiou-Yng Lee, "Low-complexity systolic array polynomial basis multiplier over GF(2m) for communication security," 2004 Cross Strait Tri-regional Radio Science and Wireless Technology Conference, pp. B3-1~6, Hsinchu, Taiwan, Sep. 2004.
    • Che Wun Chiou, Chiou-Yng Lee, Anne Lo, Yih Ming Huang, and Minor Chen, "A linear array for polynomial basis multipliers in GF(2m) fields," 2004 conference on electronic communications and applications (CECA2004) , Kaohsiung, Taiwan, May 2004.
    • Yih Ming Huang,Anne Lo, Minor Chen, Che Wun Chiou, and Chiou-Yng Lee, "Multiple channel design of analog/digital and digital/analog Converters," 2004 conference on electronic communications and applications (CECA2004) , Kaohsiung, Taiwan, May 2004.
    • Chiou-Yng Lee and Che Wun Chiou, "Flexible linear array multipliers over GF(2m) using normal basis of GF(2m)," 2004 Cross Strait Tri-regional Radio Science and Wireless Technology Conference, pp. B3-16~20, Hsinchu, Taiwan, Sep. 2004.
    • Chiou-Yng Lee and Chung-Jyi Chang, "Low-complexity linear array multipliers for optimum normal basis of type-II," The 2004 IEEE International Conference on Multimedia and EXPO (ICME 2004), Taipei, Taiwan, pp.1515-1518, June 2004. (EI)
    • Chiou-Yng Lee, "Low-complexity bit-parallel systolic multiplier over GF(2m) using irreducible xm+xn+1," 2003 International Conference on Informatics, Cybernetics, and Systems (ICICS2003), Kaohsiung, Taiwan, pp. 812-815, Dec. 2003.
    • Chiou-Yng Lee, "Low-complexity and low-latency bit-parallel systolic multipliers for optimal normal basis of Type-II," 2003 International Conference on Informatics, Cybernetics, and Systems (ICICS2003), Kaohsiung, Taiwan, pp. 806-811, Dec. 2003.
    • Yeun-Renn Ting, Erl-Huei Lu, Chiou-Yng Lee, Jau-Yien Lee, "Ringed bit-parallel systolic multipliers over a class of fields GF(2m)," 2003 International Symposium on Communications (ISCOM2003), Tao-Yuan ,Taiwan, Dec. 2003.
    • Chiou-Yng Lee, "Low-latency bit-parallel systolic multiplier for irreducible xm+xn+1 with gcd(m,n)=1," 2003 International Symposium on Communications (ISCOM2003), Tao-Yuan ,Taiwan, Dec. 2003.
    • Chiou-Yng Lee, "Low-latency bit-parallel systolic Montgomerymultipliers over GF(2m)," 2003 National Computer Symposium(NCS2003), pp. 1233-1240, Taichung, Taiwan, Dec. 2003.
    • Chiou-Yng Lee, "K-bit-parallel systolic multiplier and squarer over GF(2m)," 2003 conference on electronic communications and applications (CECA2003) , pp. 242-247, Penghu, Taiwan, May 2003.
    • Chiou-Yng Lee, Ya-Cheng Lu and Erl-Huei Lu, "Low-complexity dual basis systolic multiplier over GF(2m)," 2002 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2002) , Bali, Indonesia, pp. 367-372, Oct. 2002.(EI)
    • Chiou-Yng Lee, Erl-Huei Lu, and Jau-Yien Lee; "Bit-parallel systolic modular multipliers for a Class of GF(2m)", 15th IEEE Symposium on Computer Arithmetic (Arith-2001) , Vail, Colorado, USA , pp.51-58, June 2001(EI)
    • Chiou-Yng Lee and Erl-Huei Lu, "New bit-parallel systolic multipliers for a class of GF(2m)," 2001 IEEE International Symposium on Circuits and Systems, Sydney, Australia (ISCS-2001), vol. IV, pp. 578-581, May 2001. (EI)
    • Chiou-Yng Lee and Erl-Huei Lu, "High-speed bit-parallel systolic multipliers for a class of GF(2m)", International Symposium on VLSI Tech., System, and Application, (2001-VLSI-TSA), Hsinchu, Taiwan, pp. 291-294, April, 2001. (EI)
    • Yeun-Renn Ting, Erl-Huei Lu, and Chiou-Yng Lee, "A complex cyclic code using fast Fourier transform", 3th IEEE Signal Proc. Advances in Wireless Communication (SPAWC-2001), pp. 271-274, Taoyuan, Taiwan, April, 2001. (EI)
    • Chiou-Yng Lee, Erl-Huei Lu, and Lir-Fang Sun, "The design of a low-complexity systolic architecture for fast bit-parallel exponentiation in a class of GF(2m)", 16th IFIP Word Computer Congress on ICSP-2000, Beijing, China, Vol. 1, pp. 598-605.
    • Chiou-Yng Lee and Erl-Huei Lu, "New modular construction of low-complexity bit-parallel systolic multipliers for a class of finite fields GF(2m)," 2000 International computer Symposium, Chiayi, Taiwan, pp.149-155.
    • Chiou-Yng Lee and Erl-Huei Lu, "New bit-parallel systolic architectures for modulo(2m-1) multiplication and addition," 2000 Asia Pacific Conference on Multimedia Technology and Applications (APCMTA2000) , Kaohsiung, Taiwan, pp. 241-248.
    • 郭英傑、李秋瑩、盧而輝、李肇嚴, "有限場GF(2m)之低複雜的心臟收縮陣列式乘法與指數運算架構設計" 2000年全國電信研討會, pp.308-313。
    • Jyhi-Kong Wey, Chiou-Yng Lee, Jiu-Yang Liu; Erl-Huei Lu, " Evolution of intelligent network deployment in Taiwan's mobile networks", TENCON 99. Proceedings of the IEEE Region 10 Conference, pp. 769 -772, vol.1, 1999 (EI)
    • Erl-Huei Lu, Chiou-Yng Lee, Shao-Wei Wu, "A decoding algorithm for DEC RS codes", TENCON 99. Proceedings of the IEEE Region 10 Conference, pp. 294 -296, vol.1, 1999 (EI)

【專利】

  • 李秋瑩、盧而輝、李肇嚴,"有限場GF(2m)之低複雜的心臟收縮陣列式乘法器",2003 中華民國發明專利,發明第177839號
  • 李秋瑩、盧而輝, "有限場GF(2m)之心臟收縮陣列式雙重基底乘法器",2004 中華民國發明專利,發明第203527號

最後更新(2021/09/01)

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